[R] Xeon CPU and ATLAS
Prof Brian Ripley
ripley at stats.ox.ac.uk
Sat Mar 13 10:22:56 CET 2004
On 13 Mar 2004, Peter Dalgaard wrote:
> rossini at blindglobe.net (A.J. Rossini) writes:
>
> > > I think the difference between P4 and Xeon is the SSE1 vs SSE2 thing,
> > > so you'd want the P4SSE2 DLL, but others may be able to speak more
> > > authoritatively.
> >
> > SSE1 vs SSE2 is PIII vs PIV (so depends if your xeons are p3 or p4 (?
> > not sure if there is such a thing) based.
>
> Sure? I have
>
> turmalin:/usr/local/src/ATLAS/>ls CONFIG/ARCHS/
> 21164.tgz ConfDump.log Makefile PIIISSE1.tgz PPCG4AltiVec.tgz
> 21164GOTO.tgz CreateDef.sh P4SSE1.tgz POWER.tgz PPRO.tgz
> 21264.tgz CreateDirs.sh P4SSE2 POWER2Thin.tgz SGIIP28.tgz
> 21264GOTO.tgz CreateTar.sh P4SSE2.tgz POWER3.tgz SGIIP30.tgz
> ATHLON.tgz HP9735.tgz P5MMX.tgz PPC604.tgz SunUS2.tgz
> ATHLON3DNow2.tgz IA64Itan.tgz PII.tgz PPC604e.tgz SunUS5.tgz
> ATHLONSSE1.tgz KillDirs.sh PIII.tgz PPCG4.tgz negflt.c
>
> so it would seem that there's both P4SSE1 and PIIISSE1. However,
That's because ATLAS did not always support SSE2, and it might be
faster not to use it on some systems.
>From Intel's Xeon FAQ
http://www.intel.com/cd/ids/developer/asmo-na/eng/19250.htm
We had XMM on Pentium® III. What is the difference on Intel Xeon?
Intel Xeon offers SSE2 technology. In addition to the features of SSE,
SSE2 provides support for additional simultaneous 128-bit integer and
double-precision floating point calculations.
which seems the definitive answer re Xeons. (I am 99% sure all P4s have
the same instructions set which includes SSE2. The main Xeon differences
are that multi-processor systems are allowed and the caches are usually
larger than contemporaneous P4s.)
--
Brian D. Ripley, ripley at stats.ox.ac.uk
Professor of Applied Statistics, http://www.stats.ox.ac.uk/~ripley/
University of Oxford, Tel: +44 1865 272861 (self)
1 South Parks Road, +44 1865 272866 (PA)
Oxford OX1 3TG, UK Fax: +44 1865 272595
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